Memristor memories are resistive-based memories, where data is stored in the form of high and low resistances. Compared to capacitive based-memories, which are volatile, resistive memories are non-volatile and thus retain their state for long periods of time (on the order of years. This eliminates the need for the energy-consuming refresh cycles required by current complementary metal-oxide-semiconductor (CMOS) memories. Moreover, memristors may reduce the energy and time consumption of a startup stage of computer systems. In addition, memristors have other advantages, such as a high ON/OFF ratio and very high array density. Such high array-density may enable the memristors to be a very attractive option for future memories and solid state drives. In spite of all these attractive properties, there are many challenges that need to be addressed before the memristor genuinely replaces current memory technologies.
Memristor memory can be built using either gated or gateless memory cells, where each type of memristor has its own advantages and shortfalls. Gateless cells may provide the highest density memristor arrays, and may have a simple fabrication process, where each memory cell is just a thin film 102a located at each intersection of two crossbars 104, as shown in FIG. 1A. This is equivalent to a memristor device connecting the row and the column at their intersection, as shown in FIG. 1B. However, the gateless architecture suffers from sneak current, which is an undesired current that flows through the memory cells parallel to the desired memory cell and significantly impacts the readout operation. In addition, the sneak current significantly increases the power consumed by the memory array. Several techniques were proposed to enable a functional gateless memristor memory, such as multiport, multistage, and unfolded array readouts. However, these techniques either slow down the readout process, or impact the array density significantly.
A transistor-gated memristor array tries to mimic the classical dynamic random-access memory (DRAM) architecture, by associating a transistor 106 with each memristor memory element active film 102b, which may be implemented as an extra layer in the source or gate of the transistor (e.g., access transistor), as shown in FIG. 1C and equivalent circuit FIG. 1D. The introduced access transistor cuts the undesired sneak-paths of the current and reduces the total power consumption. However, this improvement may cause the array density to decrease as it will be dominated by the transistor footprint. While a smaller transistor may be used to maintain the high density advantage, a significant problem that arises for the smaller transistor is that the leakage current can prevent the memory array from working correctly.